This invention relates to error detection logic, and more particularly, to the verification of the error detection logic; namely, verification of parity generation and check logic.
In computer systems, data is being transferred between various components at very high rates. Usually these transfers occur in and out of a memory associated with the computer system to a central processing unit (CPU) or peripherals via a bus. In order to avoid errors, checks are generally made on the transferred data. However, for these checks to be valid, the detection circuitry must be operational.
Therefore, there is a need to provide logic which verifies the operability of these detection circuits. The verification logic included in the computer system of the present invention does not interfere with the operation of the detection circuits in a normal mode of operation.